Altera DDR Timing Wizard - Manual (Page 26)

2–14 Altera Corporation
DDR Timing Wizard User Guide November 2007
Entering and Editing Inputs to the DTW
After entering the resynchronization clock name (omitted in
Figure 2–8 ) click Skip to get to the last page of DTW.
Click Finish.
6. Add the additional assignments as listed on Step 4 of the “Design
Flow” section.
7. Compile the design and perform timing analysis.
f
For more details, refer to Chapter 3, Using the dtw_timing_analysis.tcl
Script .
Manual Flow for Other External Memory Interfaces or Source
Synchronous Systems
Use this flow when you have a custom implementation for an
Altera-supported memory interface, including the following:
■ DDR/DDR2 SDRAM
■ QDRII+/QDRII SRAM
■ RLDRAM II
1 Always implement the Altera data path and use the legacy
controller MegaWizard flow unless the feature set of the Altera
memory controller makes it impossible to do so.
The DTW Pages for DDR/DDR2 SDRAM
This section details each page in the DDR/DDR2 SDRAM interface. The
pages for QDRII+/QDRII SRAM and RLDRAM II interfaces are slightly
different than the pages for DDR/DDR2 SDRAM interfaces. The DTW
pages for QDRII+/QDRII SRAM and RLDRAM II are listed in
“The DTW
Pages for QDRII+/QDRII SRAM & RLDRAM II” on page 2–45 .
1
The following page-by-page information is based from a
controller created by the legacy controller MegaWizard but the
DTW import option is not used.
1. On the Tools menu, select Tcl Scripts. Select dtw and click Run.
2. Specify a .dwz file name to save the timing constraints for the
design and click Next.
3. Confirm the project directory and revision you want to use.
Click Next.