Altera DDR Timing Wizard - Manual (Page 70)

3–10 Altera Corporation
DDR Timing Wizard User Guide November 2007
Introduction
Table 3–3 shows the default clock names and usage if you are using
the Altera DDR2 SDRAM Controller MegaCore function.
Table 3–3. Default Clock Names and Usage in Altera DDR2 SDRAM Controller MegaCore Function Note (1) (Part 1
of 2)
Clock Usage
Timing
Analyzer
Clock Name
System clock Classic
Timing
Analyzer *:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0
TimeQuest
Timing
Analyzer *g_stratixpll_ddr_pll_inst|altpll_component|pllclk[0]
Write clock Classic
Timing
Analyzer *:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk1
TimeQuest
Timing
Analyzer *g_stratixpll_ddr_pll_inst|altpll_component|pllclk[1]
Second
resynchronization
clock Classic
Timing
Analyzer *:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk2
TimeQuest
Timing
Analyzer *g_stratixpll_ddr_pll_inst|altpll_component|pllclk[2]
CK/CK# (when
using dedicated
clock output pins) Classic
Timing
Analyzer *:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk3
TimeQuest
Timing
Analyzer *g_stratixpll_ddr_pll_inst|altpll_component|pllclk[3]
First
resynchronization
clock Classic
Timing
Analyzer *:g_stratixpll_ddr_fedbackpll_inst|altpll:altpll_component|_clk0
TimeQuest
Timing
Analyzer *g_stratixpll_ddr_fedback_pll_inst|altpll_component|pllclk[0]