Altera DDR Timing Wizard - Manual (Page 45)

Altera Corporation 2–33
November 2007 DDR Timing Wizard User Guide
Getting Started
Figure 2–23. Postamble Clock and Phase Shift Relationship in DTW and the DDR2/DDR SDRAM Controller
MegaWizard
Similar to the resynchronization clock connectivity page, clicking on
any field in this page highlights the appropriate paths in the
schematic at the bottom of the page. The schematic also changes
when you are using only one PLL to create the interface.
Click Next.
13. You must specify which PLL output clocks drive the DQS and DQ
write signals so the DTW can properly constrain the skew between
these pins.