Entering and editing inputs to the dtw, Entering and editing inputs to the dtw –6, Figure 2–2 – Altera DDR Timing Wizard User Manual
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2–6
Altera Corporation
DDR Timing Wizard User Guide
November 2007
Entering and Editing Inputs to the DTW
Figure 2–2. Launching the DDR Timing Wizard
3.
Click Run.
1
You can also launch the DTW from the command line with
the following command:
<
quartus_ii_installation_directory>/bin/quartus_sh --dtw
Entering and
Editing Inputs to
the DTW
If you use the Altera legacy controller MegaWizard as a starting point for
your memory interfaces, follow the import flow described below to enter
and edit inputs to the DTW. The legacy controller MegaWizard is the
recommended tool, and simplifies entry of the essential design
requirements. If you have an interface that is not supported by the legacy
controller MegaWizard , refer to
“Manual Flow for Other External
Memory Interfaces or Source Synchronous Systems” on page 2–14
1
The screen captures of the DTW pages shown in this section are
from the Legacy_PHY.qar design that is downloadable with
Arria GX Devices
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)