Altera Arria 10 Avalon-MM DMA - Manual (Page 66)

Signal Direction Description
• 5’b11010: Speed.Recovery
• 5’b11011: Recovery.Equalization, Phase 0
• 5’b11100: Recovery.Equalization, Phase 1
• 5’b11101: Recovery.Equalization, Phase 2
• 5’b11110: Recovery.Equalization, Phase 3
• 5’b11111: Recovery.Equalization, Done
sim_pipe_pclk_in Input This clock is used for PIPE simulation only, and is derived from
the
refclk
. It is the PIPE interface clock used for PIPE mode
simulation.
sim_pipe_rate[1:0] Input Specifies the data rate. The 2-bit encodings have the following
meanings:
• 2’b00: Gen1 rate (2.5 Gbps)
• 2’b01: Gen2 rate (5.0 Gbps)
• 2’b1X: Gen3 rate (8.0 Gbps)
txblkst
For Gen3 operation, indicates the start of a block in the transmit
direction.
txcompl0
Output Transmit compliance . This signal forces the running
disparity to negative in compliance mode (negative COM
character).
txdata0[31:0] Output Transmit data. This bus transmits data on lane .
txdatak0[3:0] Output Transmit data control . This signal serves as the control bit
for
txdata
. Bit 0 corresponds to the lowest-order byte of
rxdata
, and so on. A value of 0 indicates a data byte. A value of 1
indicates a control byte. For Gen1 and Gen2 only.
txdataskip0 Output For Gen3 operation. Allows the MAC to instruct the TX interface
to ignore the TX data interface for one clock cycle. The following
encodings are defined:
• 1’b0: TX data is invalid
• 1’b1: TX data is valid
txdeemph0 Output Transmit de-emphasis selection. The value for this signal is set
based on the indication received from the other end of the link
during the Training Sequences (TS). You do not need to change
this value.
txdetectrx0
Output Transmit detect receive . This signal tells the PHY layer to
start a receive detection operation or to begin loopback.
UG-01145_avmm_dma
2015.05.14
PIPE Interface Signals 5-25
IP Core Interfaces Altera Corporation
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