Altera Arria 10 Avalon-MM DMA - Manual (Page 104)

As this figure indicates, the IP core includes the following clock domains:
coreclkout_hip
Table 7-1: Application Layer Clock Frequency for All Combinations of Link Width, Data Rate and
Application Layer Interface Widths
The
coreclkout_hip
signal is derived from
pclk
. The following table lists frequencies for
coreclkout_hip
,
which are a function of the link width, data rate, and the width of the Application Layer to Transaction Layer
interface. The frequencies and widths specified in this table are maintained throughout operation. If the link
downtrains to a lesser link width or changes to a different maximum link rate, it maintains the frequencies it was
originally configured for as specified in this table. (The Hard IP throttles the interface to achieve a lower
throughput.)
Link Width Max Link Rate Avalon Interface Width coreclkout_hip
×8 Gen1 128 125 MHz
×4 Gen2 128 125 MHz
×8 Gen2 128 250 MHz
×8 Gen2 256 125 MHz
×4 Gen3 128 250 MHz
×4 Gen3 256 125 MHz
×8 Gen3 256 250 MHz
pld_clk
coreclkout_hip
can drive the Application Layer clock along with the
pld_clk
input to the IP core. The
pld_clk
can optionally be sourced by a different clock than
coreclkout_hip
. The
pld_clk
minimum
frequency cannot be lower than the
coreclkout_hip
frequency. Based on specific Application Layer
constraints, a PLL can be used to derive the desired frequency.
Clock Summary
Table 7-2: Clock Summary
Name Frequency Clock Domain
coreclkout_hip 62.5, 125 or 250 MHz Avalon-ST interface between the Transaction and
Application Layers.
pld_clk 125 or 250 MHz Application and Transaction Layers.
UG-01145_avmm_dma
2015.05.14
coreclkout_hip 7-5
Arria 10 Reset and Clocks Altera Corporation
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