Altera Arria 10 Avalon-MM DMA - Manual (Page 116)

• The Gen1, Gen2, and Gen3 simulation models support PIPE and serial simulation.
• For Gen3, the Altera BFM bypasses Gen3 Phase 2 and Phase 3 Equalization. However, Gen3 variants
can perform Phase 2 and Phase 3 equalization if instructed by a third-party BFM.
Related Information
PIPE Interface Signals on page 5-22
Data Link Layer
The Data Link Layer is located between the Transaction Layer and the Physical Layer. It maintains packet
integrity and communicates (by DLL packet transmission) at the PCI Express link level (as opposed to
component communication by TLP transmission in the interconnect fabric).
The DLL implements the following functions:
• Link management through the reception and transmission of DLL packets (DLLP), which are used for
the following functions:
• Power management of DLLP reception and transmission
• To transmit and receive
ACK
/
NACK
packets
• Data integrity through generation and checking of CRCs for TLPs and DLLPs
• TLP retransmission in case of
NAK
DLLP reception using the retry buffer
• Management of the retry buffer
• Link retraining requests in case of error through the Link Training and Status State Machine
(LTSSM) of the Physical Layer
9-4 Data Link Layer
UG-01145_avmm_dma
2015.05.14
Altera Corporation IP Core Architecture
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