Altera Arria 10 Avalon-MM DMA - Manual (Page 27)

Parameter Value Description
Enable burst capabilities
for RXM BAR2 ports
On/Off When you turn on this option, the BAR2 RX Avalon-
MM master is burst capable. If BAR2 is 32 bits and
Burst capable, then BAR3 is not available for other use.
If BAR2 is 64 bits, the BAR3 register holds the upper 32
bits of the address.
Address width of
accessible PCIe memory
space
20–64 Specifies the size of the PCIe memory space. The value
you specify sets the width of the TX slave address,
txs_
address
for 64-bit addresses.
Number of address pages 2, 4, 8, 16, 32, 64,
128, 256, 512
Specifies the number of consecutive address pages in the
PCI Express address domain. This parameter is only
necessary for 32-bit addresses.
Size of address pages 4 KByte–4GByte Sets the size of the PCI Express system pages. All pages
must be the same size. This parameter is only necessary
for 32-bit addresses.
Related Information
coreclkout_hip on page 7-5
Base Address Register (BAR) Settings
The type and size of BARs available depend on port type.
Table 3-3: BAR Registers
Parameter Value Description
Type Disabled
64-bit prefetchable memory
32-bit non-prefetchable memory
32-bit prefetchable memory
I/O address space If you select 64-bit prefetchable memory, 2
contiguous BARs are combined to form a 64-bit
prefetchable BAR; you must set the higher numbered
BAR to Disabled.
Defining memory as prefetchable allows contiguous
data to be fetched ahead. Prefetching memory is
advantageous when the requestor may require more
data from the same region than was originally
requested. If you specify that a memory is prefetch‐
able, it must have the following 2 attributes:
• Reads do not have side effects
• Write merging is allowed
The 32-bit prefetchable memory and I/O address
space BARs are only available for the Legacy
Endpoint.
UG-01145_avmm_dma
2015.05.14
Base Address Register (BAR) Settings 3-7
Parameter Settings Altera Corporation
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