Release information, Release information -6 – Altera Arria 10 Avalon-MM DMA User Manual
Page 10
Transaction Layer
Packet type (TLP)
(transmit support)
Avalon-ST Interface
Avalon-MM
Interface
Avalon-MM DMA
Avalon-ST Interface with SR-
IOV
Completion-
Locked (
CplLk
)
EP/RP
EP
Completion
Lock with Data
(
CplDLk
)
EP/RP
EP
Fetch and Add
AtomicOp
Request
(
FetchAdd
)
EP
The Arria 10 Avalon-MM DMA Interface for PCIe Solutions User Guide explains how to use this IP core
and not the PCI Express protocol. Although there is inevitable overlap between these two purposes, use
this document only in conjunction with an understanding of the PCI Express Base Specification.
Related Information
•
•
•
Release Information
Table 1-4: Hard IP for PCI Express Release Information
Item
Description
Version
15.0
Release Date
May 2015
Ordering Codes
No ordering code is required
Product IDs
The Product ID and Vendor ID are not required
because this IP core does not require a license.
Vendor ID
1-6
Release Information
UG-01145_avmm_dma
2015.05.14
Altera Corporation
Datasheet
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)