Altera Arria 10 Avalon-MM DMA User Manual
Page 122
The following restrictions apply when you select the embedded the DMA Descriptor Controller:
• BAR0 accesses the embedded DMA Descriptor Controller. BAR0 cannot connect to the Avalon-MM
master RX single dword interface or any other interface. If BAR0 must access the Avalon-MM master
RX interface, you must use an external DMA descriptor controller.
• The RX burst master has the following restrictions for both internal and external descriptor control‐
lers :
• The RX burst master must connect to BAR2 for 32-bit addresses.
• The RX burst master must connect to BAR2 and BAR3 for 64-bit addresses
• The Avalon-MM master RX can only issue downstream single dword requests. The following BAR
restrictions apply to this RX master:
• When using an external DMA controller, this RX master can connect to any BARs.
• When using the embedded DMA controller, this RX master can connect to BAR2-BAR5, assuming
the Avalon-MM RX burst master does not connect to BAR2-BAR3.
The RX burst master supports a maximum read request of 4096 bytes, which is the maximum allowed by
the PCI Express specification.
If you plan to modify or replace the DMA Descriptor Controller, Altera recommends that you instantiate
it separately. The following block diagram illustrates this configuration. Your descriptor controller must
interface to the DMA read and DMA write modules that are always part of the PCI Express Avalon-MM
Bridge. You may need to modify the DMA Descriptor Controller for the following reasons:
• To implement multi-channel operation
• To implement the descriptors as a linked list instead of as separate entries in a table
Figure 9-5: Avalon-MM DMA Block Diagram with Separately Instantiated DMA Descriptor Controller
Altera FPGA
Memory
Read DMA
Write DMA
Hard IP
for PCIe
RX Master
TX Slave
DMA
Descriptor
Controller
Avalon-MM Burst Master 256 Bits
Avalon-MM Master 256 Bits
Avalon-MM Master Single DWORD
Avalon-MM Slave Single DWORD
Avalon-ST Control/Status
Avalon-ST
256 Bits
PCIe Avalon-MM
Bridge
Hard IP for PCIe Using Avalon-MM Interface
with External Descriptor Controller
Qsys System
9-10
Arria 10 Avalon-MM DMA for PCI Express
UG-01145_avmm_dma
2015.05.14
Altera Corporation
IP Core Architecture