Altera Arria 10 Avalon-MM DMA User Manual
Page 24
Parameter
Value
Description
Enable byte
parity ports on
Avalon-ST
Interface
On/Off
When On, the RX and TX datapaths are parity protected.
Parity is odd. This parameter is only available for the Avalon-
ST interface.
Enable multiple
packets per cycle
for the 256-bit
interface
On/Off
When On, the 256-bit Avalon-ST interface supports the
transmission of TLPs starting at any 128-bit address
boundary, allowing support for multiple packets in a single
cycle. To support multiple packets per cycle, the Avalon-ST
interface includes 2 start of packet and end of packet signals
for the 256-bit Avalon-ST interfaces. This feature is only
supported for Gen3 ×8.
Enable configu‐
ration via
Protocol (CvP)
On/Off
When On, the Quartus II software places the Endpoint in the
location required for configuration via protocol (CvP). For
more information about CvP, click the Configuration via
Protocol (CvP) link below.
Enable credit
consumed
selection port
On/Off
When you turn on this option, the core includes the
tx_cons_
cred_sel
port. This parameter is not available for the Avalon-
MM with DMA interface.
Enable Configu‐
ration Bypass
(CfgBP)
On/Off
When you turn on this option, you can substitute a custom
Configuration Space implemented in soft logic for the
Configuration Space included in the Hard IP for PCI Express.
This option is only available for the Avalon-ST interface.
Enable dynamic
reconfiguration
of PCIe read-only
registers
On/Off
When On, you can use the Hard IP reconfiguration bus to
dynamically reconfigure Hard IP read-only registers.
For more information refer to
on page 5-20.
Enable Altera
Debug Master
Endpoint
(ADME)
On/Off
When On, you can use the Altera System Console to read and
write the embedded Arria 10 Native PHY registers.
Related Information
Provides information about the ADME feature for Arria 10 devices.
3-4
System Settings
UG-01145_avmm_dma
2015.05.14
Altera Corporation
Parameter Settings