Altera Arria 10 Avalon-MM DMA - Manual (Page 43)

Figure 5-1: Signals When Descriptor Controller Is Embedded in the Avalon-MM Bridge
tx_out0[ -1:0]
rx_in0[-1:0]
Serial Data
Hard IP for PCI Express Using Avalon-MM with DMA
TxsWriteData_i[-1:0]
TxsRead_i
TxsWrite_i
TxsChipSelect_i
TxsAddress_i[-1:0]
TxsByteEnable[3:0]
TxsReadData_o[-1:0]
TxsReadDataValid_o
TxsWaitRequest_o
TX Slave:
Allows FPGA to Send Single
DWord Reads or Writes
from FPGA to Root Port
RxmRead_o
RdDCMAddress_0[63:0]
RdDCMByteEnable_o[3:0]
RdDCMReadDataValid_i
RdDCMRead Data_i[31:0]
RdDCMRead_o
RdDCMWaitRequest_i
RdDCMWriteData_o[31:0]
RdDCMWrite_o
RxmWrite_o
RxmAddress_o[-1:0]
RxmBurstCount_o[5:0]
RxmByteEnable_o[-1:0]
RxmWriteData_o[31:0]
RxmReadData_i[31:0]
RxmReadDataValid_i
RxmWaitRequest_i
CraWriteData_i[31:0]
CraWaitRequest_o
CraChipSelect_i
CraByteEnable_i[3:0]
CraAddress_i[13:0]
CraRead_i
CraWrite_i
CraReadData_o[31:0]
Host Access to
Control/Status Regs
of Avalon-MM Bridge
MsiIntfc_o[81:0]
MsixIntfc_o[15:0]
MsiControl_o[15:0]
intx_req_i
intx_ack_o
RdDmaWrite_o
RdDmaAddress_o[63:0]
RdDmaWriteData[-1:0]
RdDmaBurstCount_o[-1:0]
RdDmaByteEnable_o[ -1:0]
RdDmaWaitRequest_i
Read DMA Avalon-MM :
Writes data from Host
memory to FPGA memory.
WrDmaRead_o
WrDmaAddress_o[63:0]
WrDmaReadData_i[-1:0]
WrDmaBurstCount_o[ -1:0]
WrDmaWaitRequest_i
WrDmaReadDataValid_i
Write DMA Avalon-MM :
Fetch data from FPGA memory
before sending to Host memory.
MSI and MSI-X
Interface
npor
nreset_status
pin_perst
Reset
Clocks
refclk
coreclkout_hip
Avalon-MM Master
Rd Descriptor Controller
Avalon-MM Master
Drives TX Slave to
Perform Single DWord
Transactions
to the Hard IP for PCIe
for Host to Access
Registers and Memory
1 RX Master for Each
BAR
Test and
Mode Control
test_in[31:0]
simu_mode_pipe
Gen3 PIPE
(simulation
only)
currentcoeff0[17:0]
currentrxpreset0[2:0]
eidleinfersel[2:0]
phystatus0
powerdown0[1:0]
rate[1:0]
rxblkst0
rxdata0[31:0]
rxdatak[3:0]
rxdataskip
rxelecidle0
rxpolarity
rxstatus0[2:0]
rxsynchd0[1:0]
rxvalid0
sim_ltssmstate[4:0]
sim_pipe_pclk_in
sim_pipe_rate[1:0]
txblkst
txcompl0
txdata0[31:0]
txdatak0[3:0]
txdataskip
txdeemph0
txdetectrx0
txelecidle0
txmargin0
txswing0
txsynchd0[1:0]
WrDCMAddress_o[63:0]
WrDCMByteEnable_o[3:0]
WrDCMReadDataValid_i
WrDCMRead Data_i[31:0]
WrDCMRead_o
WrDCMWaitRequest_i
WrDCMWriteData_o[31:0]
WrDCMWrite_o
WrDTSAddress_i[7:0]
WrDTSBurstCount_i[4:0]
WrDTSChipSelect_i
WrDTXWaitRequest_o
WrDTSWriteData_i[-1:0]
WrDTSWrite_i
Wr Descriptor Controller
Avalon-MM Master
Drives TX Slave to
Perform Single DWord
Transactions
to the Hard IP for PCIe
Descriptor Controller
Avalon-MM Slave
Receives Requested
Write Descriptors from the
DMA Read Master
Descriptor Controller
Avalon-MM Slave
Receives Requested
Read Descriptors from the
DMA Read Master
RdDTSAddress_i[7:0]
RdDTSBurstCount_i[4:0]
RdDTSChipSelect_i
RdDTSWaitRequest_o
RdDTSWriteData_o[-1:0]
RdDTSWrite_i
Hard IP
Reconfiguration
(Optional)
hip_reconfig_clk
hip_reconfig_rst_n
hip_reconfig_address[9:0]
hip_reconfig_read
hip_reconfig_readdata[15:0]
hip_reconfig_write
hip_reconfig_writedata[15:0]
hip_reconfig_byte_en[1:0]
ser_shift_load
interface_sel
5-2 Arria 10 DMA Avalon-MM DMA Interface to the Application Layer
UG-01145_avmm_dma
2015.05.14
Altera Corporation IP Core Interfaces
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