Altera Arria 10 Avalon-MM DMA - Manual (Page 128)

Date Version Changes Made
• Removed Migration and TLP Format appendices, and added new
appendix Frequently Asked Questions on page 11-1.
• Updated information in SDC Timing Constraints on page 10-2.
• Removed list of static example designs from Example Designs on
page 1-7. You can derive the list from the installation directory
where example designs are available.
• Fixed minor errors and typos.
2014.12.15 14.1 Made the following changes to the Arria 10 user guide:
• In the Getting Started chapter, corrected directory path for the
simulation.
• Added the fact that the RX Burst Master only support dword
granularity.
• Added definitions for
test_in[2]
,
test_in[6]
and
test_in[7]
.
• Added instructions for Quartus II compilation.
2014.08.18 14.0 Arria 10
Made the following changes to the Arria 10 Avalon-MM DMA for
PCI Express IP core:
• Revised programming model for the Descriptor Controller.
• Added simulation log file,
altpcie_monitor_a10_dlhip_tlp_file_log.log
,
that is automatically generated in your simulation directory. To
simulate in the Quartus II 14.0 software release, you must
regenerate your IP core to create the supporting monitor file the
generates altpcie_monitor_a10_dlhip_tlp_file_log.log . Refer to
Understanding Simulation Dump File Generation for details.
• Added support for either 128- or 256-bit interface to the Applica‐
tion Layer.
• Added support for 64-bit addressing, making address translation
unnecessary.
• Removed Channel Placement for PCIe in Arria 10 Devices. Please
contact your Altera sales representative for PLL and channel
usage.
• Added support for optional bursting RX Master for BAR2.
• Revised Read DMA Example and Software Program for Simulta‐
neous Read and Write DMA to work with revised programming
model for the Descriptor Controller.
B-2 Revision History for the Avalon-MM Interface with DMA
UG-01145_avmm_dma
2015.05.14
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