Altera Arria 10 Avalon-MM DMA - Manual (Page 115)

Top-Level Interfaces
Avalon-MM DMA Interface
An Avalon-MM interface with DMA connects the Application Layer and the Transaction Layer. This
interface includes high-performance, burst capable Read DMA and Write DMA modules. This variant is
available for the following Endpoint configurations:
• Gen1 x8
• Gen2 x2
• Gen2 x4
• Gen2 x8
• Gen3 x2
• Gen3 x4
• Gen3 x8
Related Information
Arria 10 DMA Avalon-MM DMA Interface to the Application Layer on page 5-1
Clocks and Reset
The PCI Express Base Specification requires an input reference clock, which is called
refclk
in this design.
The PCI Express Base Specification stipulates that the frequency of this clock be 100 MHz.
The PCI Express Base Specification also requires a system configuration time of 100 ms. To meet this
specification, IP core includes an embedded hard reset controller. This reset controller exits the reset state
after the I/O ring of the device is initialized.
Interrupts
The Hard IP for PCI Express offers the following interrupt mechanisms:
• Message Signaled Interrupts (MSI)— MSI uses the Transaction Layer's request-acknowledge
handshaking protocol to implement interrupts. The MSI Capability structure is stored in the Configu‐
ration Space and is programmable using Configuration Space accesses.
• MSI-X—The Transaction Layer generates MSI-X messages which are single dword memory writes. In
contrast to the MSI capability structure, which contains all of the control and status information for
the interrupt vectors, the MSI-X Capability structure points to an MSI-X table structure and MSI-X
PBA structure which are stored in memory.
Related Information
MSI Interrupts for Endpoints on page 5-19
PIPE
The PIPE interface implements the Intel-designed PIPE interface specification. You can use this parallel
interface to speed simulation; however, you cannot use the PIPE interface in actual hardware.
UG-01145_avmm_dma
2015.05.14
Top-Level Interfaces 9-3
IP Core Architecture Altera Corporation
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