Compiling the design, Compiling the design -6 – Altera Arria 10 Avalon-MM DMA User Manual
Page 19
a. In the Family list, select Arria 10 (GX/SX/GT).
b. In the Devices list, select All.
c. In the Available devices list, select the appropriate device. For Arria 10 ES2 development kits, select
10AX115S1F45I3SGE2.
9. Click Next to close this page and display the EDA Tool Settings page.
10.From the Simulation list, select ModelSim. From the Format list, select the HDL language you intend
to use for simulation.
11.Click Next to display the Summary page.
12.Check the Summary page to ensure that you have entered all the information correctly.
13.Click Finish.
14.Save your project.
Adding Virtual Pin Assignment to the Quartus II Settings File (.qsf)
To compile successfully you must add a virtual pin assignment statement for the PIPE interface to
your
.qsf
file. The PIPE interface is useful for debugging, but is not a top-level interface of the IP core.
1. Browse to the synthesis directory that includes the
.qsf
for your project,
avmm256_integrated/synth
2. Open
ep_g3x8_avmm256_integrated.qsf
.
3. Add the following assignment statement:
set_instance_assignment -name VIRTUAL_PIN ON -to pcie_a10_hip_0_hip_pipe_*
4. Save the
.qsf
file.
Compiling the Design
1. Before compiling, you need to make a few changes to your top-level Verilog HDL file to create a design
that you can successfully download to a PCB.
a. In the
, open
ep_g3x8_avmm256_integrated.v.
b. Comment out the declaration for
pcie_a10_hip_0_hip_ctrl_test_in
.
c. Add a wire
[31:0] pcie_a10_hip_0_hip_ctrl_test_in
declaration to the same the same file.
d. Assign
pcie_a10_hip_0_hip_ctrl_test_in
= 0x000000A8.
e. Connect
pcie_a10_hip_0_hip_ctrl_test_in
to the
test_in
port on the Arria 10 Hard IP for
PCI Express instance.
2. On the Quartus II Processing menu, click Start Compilation.
3. After compilation, expand the TimeQuest Timing Analyzer folder in the Compilation Report. Note
whether the timing constraints are achieved in the Compilation Report.
If your design does not initially meet the timing constraints, you can find the optimal Fitter settings for
your design by using the Design Space Explorer. To use the Design Space Explorer, click Launch Design
Space Explorer on the Tools menu.
2-6
Adding Virtual Pin Assignment to the Quartus II Settings File (.qsf)
UG-01145_avmm_dma
2015.05.14
Altera Corporation
Getting Started with the Avalon-MM DMA