Altera Arria 10 Avalon-MM DMA - Manual (Page 33)

Parameter Value Description
Endpoint L1
acceptable
latency
Maximum of 1 us
Maximum of 2 us
Maximum of 4 us
Maximum of 8 us
Maximum of 16 us
Maximum of 32 us
No limit This value indicates the acceptable latency that an Endpoint
can withstand in the transition from the L1 to L0 state. It is an
indirect measure of the Endpoint’s internal buffering. It sets
the read-only value of the Endpoint L1 acceptable latency field
of the
Device Capabilities Register
.
This Endpoint does not support the L0s or L1 states. However,
a switched system may include links connected to switches
that have L0s and L1 enabled. This parameter is set to allow
system configuration software to read the acceptable latencies
for all devices in the system and the exit latencies for each link
to determine which links can enable Active State Power
Management (ASPM). This setting is disabled for Root Ports.
The default value of this parameter is 1 µs. This is the safest
setting for most designs.
PCIe Address Space Settings
Table 3-10: PCIe Address Space Settings
Parameter Value Default Value Description
Address
width of
accessible
PCIe
Memory
space
20–64
32
Specifies the width of the TX Slave Module Avalon-MM
address. This address is used unchanged as the PCIe
address.
UG-01145_avmm_dma
2015.05.14
PCIe Address Space Settings 3-13
Parameter Settings Altera Corporation
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