Altera 50G Interlaken MegaCore Function User Manual
50g interlaken megacore function user guide
Table of contents
Document Outline
- 50G Interlaken MegaCore Function User Guide
- Contents
- 1. About This MegaCore Function
- 2. Getting Started With the 50G Interlaken IP Core
- Installing and Licensing IP Cores
- Specifying the 50G Interlaken IP Core Parameters and Options
- Files Generated for Arria V GZ and Stratix V Variations
- Files Generated for Arria 10 Variations
- Simulating the50G Interlaken IP Core
- Integrating Your IP Core in Your Design
- Compiling the Full Design and Programming the FPGA
- 3. 50G Interlaken IP Core Parameter Settings
- 4. Functional Description
- Interfaces Overview
- High Level Block Diagram
- Clocking and Reset Structure for IP Core
- Interleaved and Packet Modes
- 50G Interlaken IP Core Transmit Path
- 50G Interlaken IP Core Receive Path
- 5. 50G Interlaken MegaCore Function Signals
- 6. 50G Interlaken IP Core Register Map
- 7. 50G Interlaken IP Core Testbench
- 8. 50G Interlaken IP Core Test Features
- 9. Advanced Parameter Settings
- 10. Out-of-Band Flow Control in the 50G Interlaken MegaCore Function
- A. Performance and Fmax Requirements for 40G Ethernet Traffic
- B. Additional Information