Counter reset bits, Include temp sense, Rxfifo address width – Altera 50G Interlaken MegaCore Function User Manual
Page 80: Counter reset bits -2, Include temp sense -2, Rxfifo address width -2
Counter Reset Bits
The Counter Reset Bits parameter (
CNTR_BITS
) specifies the counter configuration for the IP core
internal reset sequence.
This parameter is not available in IP core variations that target an Arria 10 device. In Arria 10 variations,
the size of the reset counters in the internal reset controller is set when the IP core is generated.
For simulation, set this parameter to the value of 6. For hardware testing, set this parameter to the value of
20.
The default value of this parameter is 20.
Related Information
Modifying Hidden Parameter Values
on page 9-4
Include Temp Sense
The Include Temp Sense parameter specifies whether the IP core includes logic to sense the device’s case
temperature. If the value is set to 1, the IP core is configured with internal temperature sensing. If the
value is set to 0, this logic is synthesized away.
This parameter is not available in IP core variations that target an Arria 10 device.
The default value of this parameter is 1.
Related Information
Modifying Hidden Parameter Values
on page 9-4
RXFIFO Address Width
The RXFIFO Address Width parameter specifies the number of bits in the address (offset) of an entry in
the RX Reassembly FIFO. The number of bits is log
2
of the depth of this FIFO. Each RX Reassembly FIFO
entry is a 64-bit word.
The default value for the RXFIFO Address Width parameter is 12, specifying this FIFO can hold 2
12
(==4K) 64-bit words. Adjusting this parameter may affect your ability to close timing for your design.
However, you can adjust this parameter subject to the successful closure of the timing.
Related Information
Modifying Hidden Parameter Values
on page 9-4
SWAP_TX_LANES and SWAP_RX_LANES (Data Word Lane Swapping)
The 50G Interlaken IP core supports a lane reversal feature (lane swapping). Lane swapping parameters
determine the order in which blocks are distributed and gathered from the lanes. The 50G Interlaken IP
core provides the following two options for the lane order:
• Straight Lane order. The transmitter sends Interlaken blocks sequentially across the lanes starting with
the top lane, ending with Lane 0. The receiver takes in Interlaken blocks starting with the top lane,
ending with Lane 0.
9-2
Counter Reset Bits
UG-01140
2015.05.04
Altera Corporation
Advanced Parameter Settings