Altera 50G Interlaken MegaCore Function - Manual (Page 7)

Device Family Support
Other device families No support
IP Core Verification
Before releasing a version of the 50G Interlaken IP core, Altera runs comprehensive regression tests in the
current version of the Quartus ® II software. These tests use standalone methods. These files are tested in
simulation and hardware to confirm functionality. Altera tests and verifies the 50G Interlaken IP core in
hardware for different platforms and environments.
Constrained random techniques generate appropriate stimulus for the functional verification of the IP
core. Functional coverage metrics measure the quality of the random stimulus, and ensure that all
important features are verified.
Performance and Resource Utilization
Table 1-4: 50G Interlaken MegaCore Function FPGA Resource Utilization
The table shows results obtained using the Quartus II software v13.1 and v13.1 Arria 10 edition releases for the
following devices:
• Arria 10 device 10AX115S2F45I2SGES
• Arria V GZ device 5AGZE1H2F35I3
• Stratix V GX device 5SGXMA7N2F45I3
The results in this table do not include the out-of-band flow control block.
The numbers of ALMs and logic registers are rounded up to the nearest 100. The numbers of ALMs, before
rounding, are the ALMs needed numbers from the Quartus II Fitter Report.
Device
Resource Utilization
ALMs
Logic Registers
M20K Blocks
Primary Secondary
Arria 10 9900 20600 1500 17
Arria V GZ 9800 20800 1600 17
Stratix V GX 9800 20700 1700 17
Stratix V GT 9800 20700 1600 17
UG-01140
2015.05.04
IP Core Verification 1-3
About This MegaCore Function Altera Corporation
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