Altera 50G Interlaken MegaCore Function - Manual (Page 75)

receive PRBS input, you can check the receive PRBS status in the 50G Interlaken IP core PRBS status
registers (
RX_PRBS_DONE, RX_PRBS_ERR,
and
RX_PRBS_COUNT
).
After your testing is complete, you must reset these register bits to their default values to enable normal
operation.
Related Information
• 50G Interlaken IP Core Register Map on page 6-1
Describes the PRBS status registers.
• PRBS Generation and Validation on page 8-2
Lists the supported PRBS polynomials.
• Altera Transceiver PHY IP Core User Guide
Setting up PRBS Mode in Arria 10 Devices
To enable the IP core to generate PRBS output, for each Interlaken lane, you must program the relevant
hard PCS registers to enable the PRBS generator clock, to set the test_enable bit, and to select the PRBS
polynomial. To enable the IP core to receive PRBS input, for each Interlaken lane, you must program the
relevant hard PCS registers to enable the PRBS receiver clock and to select the expected PRBS polynomial,
in addition to some bookkeeping tasks. If you perform your PRBS testing in loopback mode, you must
enable the IP core to both generate and receive PRBS sequences. After you set the hard PCS registers for
PRBS mode, you must perform a soft reset of the transceiver.
This section describes the register values you must program. For instructions to program the registers that
activate the PRBS test feature in your Arria 10 50G Interlaken IP core, refer to the hard PCS register
information in the Arria 10 Transceiver PHY User Guide. You program the hard PCS registers using the
50G Interlaken IP core Arria 10 transceiver reconfiguration interface.
Table 8-3: Programming the Hard PCS Registers in Arria 10 Devices
To turn on the PRBS feature in the hard PCS for IP core variations that target an Arria 10 device, you must
program the following hard PCS registers in the order shown, for each of the TX and RX sides. These registers are
not accessible using the 50G Interlaken IP core management interface. You must access these registers through
the Arria 10 transceiver reconfiguration interface of the 50G Interlaken IP core.
Ensure you set these register bits using a read-modify-write register access sequence (per register), to avoid
modifying the other register fields.
TX Register Offset Bits Meaning Action
1 0x6
[2:0] TX test enable Set this field to the value of 3'b100 to enable
the PRBS pattern generator in the
transmitter.
[3] PRBS width select Set this bit to the value of 0 to specify that
the PRBS width is 64 bits.
[7:6] Enable TX PRBS clock Set this field to the value of 2'b01 to enable
the TX PRBS clock.
8-4 Setting up PRBS Mode in Arria 10 Devices
UG-01140
2015.05.04
Altera Corporation 50G Interlaken IP Core Test Features
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