Altera 50G Interlaken MegaCore Function User Manual
Page 54
Signal Name
Direction Width
(Bits)
Description
irx_err
Output
1
Indicates an errored packet. This signal is valid only when both
irx_num_valid[2:0]
and
irx_eopbits[3:0]
are non-zero. When a
CRC24 or other error occurs, the 50G Interlaken IP core asserts this
signal for all open channel packets to label them all as errored packets,
because the IP core cannot assign the error to a specific channel.
Related Information
•
50G Interlaken IP Core RX Errored Packet Handling
Describes the behavior of the
irx_err
signal.
•
on page 3-2
Describes the parameter to select Packet or Interleaved mode.
•
on page 4-7
Describes the Packet and Interleaved modes.
50G Interlaken IP Core Interlaken Link and Miscellaneous Interface
Signals
Table 5-4: 50G Interlaken IP Core SERDES Signals, Burst Parameter Signals, and Real Time Status Signals
Signal Name
Direction
Width (Bits)
Description
SERDES Pins
rx_pin
Input
Number of lanes
Receiver SERDES data pin on the RX Interlaken
link.
tx_pin
Output
Number of lanes
Transmit SERDES data pin on the TX
Interlaken link.
TX Burst Control Settings
burst_max_in
Input
4
Encodes the BurstMax parameter for the IP
core. The actual value of the BurstMax
parameter must be a multiple of 64 bytes. While
traffic is present, this input signal should
remain static. However, when no traffic is
present, you can modify the value of the
burst_
max_in
signal to modify the BurstMax value of
the IP core.
The 50G InterlakenIP core supports the
following valid values for this signal:
2: 128 bytes
4: 256 bytes
5-8
50G Interlaken IP Core Interlaken Link and Miscellaneous Interface Signals
UG-01140
2015.05.04
Altera Corporation
50G Interlaken MegaCore Function Signals