50g interlaken ip core tx transmit buffer, 50g interlaken ip core tx mac, 50g interlaken ip core tx pcs – Altera 50G Interlaken MegaCore Function User Manual
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50G Interlaken IP Core TX Transmit Buffer
The 50G Interlaken MegaCore function TX transmit buffer performs the following function:
• Aligns the incoming user application data,
itx_data
, in the IP core internal format.
50G Interlaken IP Core TX MAC
The 50G Interlaken MegaCore function TX MAC performs the following functions:
• Inserts burst and idle control words in the incoming data stream. Burst delineation allows packet
segmentation in the Interlaken protocol.
• Performs flow adaption of the data stream, repacking the data to ensure the maximum number of
words is available on each valid clock cycle.
• Calculates and inserts CRC24 bits in all burst and idle words.
• Inserts calendar data in all burst and idle words.
• Stripes the data across the PCS lanes. Configurable order, default is MSB of the data goes to lane 0.
• Buffers data between the application and the TX PCS block in the TX FIFO buffer. The TX PCS block
uses the FIFO buffer to recover bandwidth when the number of words delivered to the transmitter is
less than the full width.
50G Interlaken IP Core TX PCS
TX PCS logic is an embedded hard macro and does not consume FPGA soft logic elements.
The 50G Interlaken MegaCore function TX PCS block performs the following functions for each lane:
• Inserts the meta frame words in the incoming data stream.
• Calculates and inserts the CRC32 bits in the meta frame diagnostic words.
• Scrambles the data according to the scrambler seed and the protocol-specified polynomial.
• Performs 64B/67B encoding.
50G Interlaken IP Core TX PMA
The 50G Interlaken MegaCore function TX PMA serializes the data and sends it out on the Interlaken
link.
50G Interlaken IP Core Receive Path
The 50G Interlaken MegaCore function receives data on the Interlaken link, monitors and removes
Interlaken overhead, and provides user data to the application.
50G Interlaken IP Core Receive User Data Interface Examples
The following examples illustrate how to use the Altera 50G Interlaken IP core RX user data interface:
50G Interlaken IP Core Receiver Side Example
on page 4-15
4-14
50G Interlaken IP Core TX Transmit Buffer
UG-01140
2015.05.04
Altera Corporation
Functional Description