Altera 50G Interlaken MegaCore Function - Manual (Page 60)

Device Dependent Signals
Some of the 50G Interlaken MegaCore function signals depend on the device that your variation targets.
Variations that target an Arria V device or a Stratix V device have an interface to connect to an Altera
Transceiver Reconfiguration Controller that you must instantiate outside the 50G Interlaken IP core for
successful functioning in hardware. Variations that target an Arria 10 device have Arria 10-specific
requirements to support the Arria 10 transceivers. The following 50G Interlaken IP core interfaces are
device specific:
Transceiver Reconfiguration Controller Interface Signals on page 5-14
Arria 10 External PLL Interface Signals on page 5-15
Arria 10 Transceiver Reconfiguration Interface Signals on page 5-15
Transceiver Reconfiguration Controller Interface Signals
50G Interlaken IP core variations that target an Arria V or a Stratix V device require an external reconfi‐
guration controller to function correctly in hardware. 50G Interlaken IP core variations that target an
Arria 10 device include a reconfiguration controller block and do not require an external reconfiguration
controller.
Table 5-6: 50G Interlaken IP Core Arria V and Stratix V Transceiver Reconfiguration Controller Interface
Signals
Signal Name Direction Width
(Bits)
Description
reconfig_to_xcvr
Input 70 bits
per
reconfi‐
guration
interface.
Bus from the external transceiver reconfiguration
controller to the 50G Interlaken IP core. The bus
includes signals fro multiple transceiver reconfigura‐
tion interfaces. The reconfiguration controller has one
interface to control each transceiver channel (one per
Interlaken lane) plus one interface to control each TX
PLL configured in the IP core. The width of each
reconfiguration controller output reconfiguration
interface is 70 bits.
reconfig_from_xcvr
Output 46 bits
per
reconfi‐
guration
interface
Bus to the external transceiver reconfiguration
controller from the 50G Interlaken IP core. The bus
includes signals for multiple reconfiguration
interfaces of the transceiver reconfiguration
controller. The reconfiguration controller has one
interface for each transceiver channel (one per
Interlaken lane) plus one interface for each TX PLL
configured in the IP core. The width of each reconfi‐
guration controller input reconfiguration interface is
46 bits.
5-14 Device Dependent Signals
UG-01140
2015.05.04
Altera Corporation 50G Interlaken MegaCore Function Signals
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