Altera 50G Interlaken MegaCore Function - Manual (Page 48)

Signal Name Direction Width
(Bits)
Description
clk_rx_common
Output 1 Master recovered lane clock. The Interlaken specifica‐
tion requires all incoming lanes to run at the same
frequency.
tx_usr_clk
Input 1 Transmit side user data interface clock. To achieve 40
Gbps Ethernet traffic throughput, you must run this
clock at a minimum frequency of 200 MHz.
By default, you must drive this clock at 250 MHz. To
change the input clock frequency, you must first
modify the value of the
TX_USR_CLK_MHZ
advanced
parameter to the new frequency. The allowed range of
frequencies you can specify is 200 MHz to 300 MHz.
rx_usr_clk
Input 1 Receive side user data interface clock. To achieve 40
Gbps Ethernet traffic throughput, you must run this
clock at a minimum frequency of 200 MHz.
By default, you must drive this clock at 250 MHz. To
change the input clock frequency, you must first
modify the value of the
TX_USR_CLK_MHZ
advanced
parameter to the new frequency. The allowed range of
frequencies you can specify is 200 MHz to 300 MHz.
mm_clk Input
1
Management clock. Clocks the register accesses. It is
also used for clock rate monitoring and some analog
calibration procedures. You must run this clock at a
frequency in the range of 100 MHz–125 MHz.
reconfig_clk Input
1 Clocks the Arria 10 transceiver reconfiguration
interface. This clock is available only in IP core
variations that target an Arria 10 device. You should
run this clock at a frequency of 100 MHz.
Related Information
Performance and Fmax Requirements for 40G Ethernet Traffic on page 11-1
Explains the
tx_usr_clk
and
rx_usr_clk
frequency requirements.
50G Interlaken IP Core Reset Interface Signals
Table 5-2: 50G Interlaken IP Core Reset Interface
Signal Name Direction Width
(Bits)
Description
50G Interlaken IP Core Reset Signals
5-2 50G Interlaken IP Core Reset Interface Signals
UG-01140
2015.05.04
Altera Corporation 50G Interlaken MegaCore Function Signals
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