Altera 50G Interlaken MegaCore Function - Manual (Page 70)

Testbench Simulation Behavior
During simulation, the 50G Interlaken IP core testbench performs the following actions:
1. Resets the 50G Interlaken IP core.
2. After the reset sequence completes, sends a sequence of Interlaken packets of pseudo-random sizes
with predefined data in the payload to the TX user data transfer interface of the IP core. This action
continues for a preset amount of time.
3. Performs a sequence of register read and write operations to demonstrate register access.
4. Resets the 50G Interlaken IP core again.
5. After the reset sequence completes, sends an additional sequence of Interlaken packets of the same
type as in Step 2.
6. Completes the sequence of packets and reports success or failure.
The testbench is not parameterizable — you cannot modify the packet sequence that the testbench
generates for a specific DUT. However, Altera provides the testbench files in cleartext format, and you can
modify the testbench for your own testing purposes.
The packet checker included in the testbench provides the following basic packet checking capabilities:
• Checks that the transmitted packet sequence is not violated
• Checks that the received data matches expected values
Running the Testbench With the Example Design
Perform the following steps to simulate the testbench example:
1.
Setting Up the Testbench Example on page 7-3
2. Simulating the Example Design on page 7-3
Setting Up the Testbench Example
When you generate your 50G Interlaken IP core, if you specify Verilog HDL IP core models, the resulting
file structure includes the example design and the testbench.
Related Information
Specifying the 50G Interlaken IP Core Parameters and Options on page 2-2
Provides instructions to generate the DUT.
Simulating the Example Design
Altera provides simulation scripts for simulating the testbench in the Mentor Graphics Modelsim SE
simulator. However, you can write your own scripts to simulate the testbench in other Altera-supported
simulators. Your script should check that the SOP and EOP counts match after simulation is complete.
To simulate the example design using the Altera-provided scripts, perform the following steps:
1. Ensure IP core generation is complete.
2. Start the Mentor Graphics ModelSim-SE simulation tool.
3. Change directory to the following folder, which contains the generated testbench:
UG-01140
2015.05.04
Testbench Simulation Behavior 7-3
50G Interlaken IP Core Testbench Altera Corporation
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