Altera 50G Interlaken MegaCore Function User Manual
Page 92
Date
ACDS Version
Changes Made
• Added information about turning on and off loopback mode in two new
sections, External Loopback Mode and Internal Serial Loopback Mode, in IP
Core Test Features chapter.
• Clarified that Counter Reset Bits is the
CNTR_BITS
advanced parameter, in
Counter Reset Bits section.
• Added new advanced parameter,
TX_USR_CLK_MHZ
, that specifies the required
frequency of the two input clocks
tx_usr_clk
and
rx_usr_clk
. Added new
section in Advanced Parameter Settings chapter, and clarified required
frequencies in 50G Interlaken IP Core Clock Interface Signals section. This
advanced parameter is included in the IP core version 14.0 and later.
• Corrected instructions to modify the
USE_ATX
advanced parameter by moving
the parameter to the correct list in Modifying Hidden Parameter Values
section.
• Clarified that the testbench and example design are generated only if you
specify the IP core synthesis and simulation models are in Verilog HDL. The
IP core does not support VHDL models, despite the fact that in the IP core
v14.0 and later, the parameter editor appears to offer that option.
• Fixed assorted typos and formatting issues.
Decem
ber
2013
13.1 Arria 10
Edition
(2013.12. 02)
• Added preliminary support for Arria 10 devices.
• Documented features of new Arria 10 variations:
• User logic must configure external PLLs.
• IP core includes reconfiguration controller.
• IP core includes new Avalon-MM interface to program Arria 10 Native
PHY IP core registers.
• IP core does not support all of the hidden parameters.
• IP core does not support temperature register and other registers related to
unsupported parameters.
• IP core provides a different process to enable the PRBS and CRC32 error
injection testing features in Arria 10 variations.
• Corrected recommended simulation value for Meta frame length in words
parameter, from 64 (an unsupported value) to 128 (the minimum supported
value).
Novem
ber
2013
13.1
(2013.11.04)
• Updated IP core generation instructions to indicate the MegaWizard Plug-In
Manager no longer prompts the user to generate or not generate the example
design. Instead, the example design is generated in all cases.
• Provided additional information about
TEMP_SENSE
register.
• Corrected typo in width of
itx_hungry
signal.
• Modified introduction of resource utilization information to clarify that the
numbers do not include the out-of-band flow control block.
• Added OpenCore Plus feature support in Installation and Licensing section.
May
2013
13.0
Initial release.
B-2
Document Revision History
UG-01140
2015.05.04
Altera Corporation
Additional Information