Altera 50G Interlaken MegaCore Function - Manual (Page 71)

a. _sim/ilk_core_50g/testbench for Arria V GZ and Stratix V IP core variations.
b. /ilk_core_50g_ /sim/testbench for Arria 10 IP core variations.
4. Type the following command:
do vlog.do
The testbench generates a series of packets on the IP core TX user data transfer interface, loops the
resulting Interlaken data transmissions back to the IP core on the Interlaken link, and checks the
packets that the IP core generates on the RX user data transfer interface. After simulation completes, a
success or failure notice displays.
7-4 Simulating the Example Design
UG-01140
2015.05.04
Altera Corporation 50G Interlaken IP Core Testbench
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