Altera 50G Interlaken MegaCore Function User Manual
Page 44
following clock cycle, labeled with data value d3, the 50G Interlaken IP Core holds the following values on
critical output signals:
•
itx_num_valid[2:0]
at the value of 3'b011 to indicate the current data symbol contains three 64-bit
words of valid data.
•
itx_eopbits[3]
high to indicate the current cycle is an EOP cycle.
•
itx_eopbits[2:0]
at the value of 3'b011 to indicate that only three bytes of the final valid data word
are valid data bytes.
This signal behavior, in the absence of the
irx_err
flag, would correctly transfer a data packet with the
total packet length of 83 bytes from the 50G Interlaken IP Core.
However, the 50G Interlaken IP Core marks the packet as errored by asserting the
irx_err
signal, even
though the
irx_eopbits
signal would appear to indicate the packet is valid.
The application is responsible for discarding the errored packet when it detects that the IP core has
asserted the
irx_err
signal.
Following the corrupted packet, the IP core waits two idle cycles and then transfers a valid 75-byte packet.
Related Information
•
50G Interlaken IP Core Packet Mode Operation Example
on page 4-10
The first data transfer in the current example is the receiver interface equivalent of the transmitter
interface transfer example described at this link.
•
In-Band Calendar Bits on the 50G Interlaken IP Core Receiver User Data Interface
on page 4-18
Description of in-band calendar bits on the RX user data transfer interface.
In-Band Calendar Bits on the 50G Interlaken IP Core Receiver User Data Interface
The 50G Interlaken IP core receiver logic decodes incoming control words (both Burst control words and
Idle control words) on the incoming Interlaken link, extracts the calendar pages from the In-Band Flow
Control bits, and assembles them into the
irx_calendar
output signal.
The 50G Interlaken IP core receives the most significant calendar page in a control word with the Reset
Calendar bit set, indicating the beginning of the calendar page sequence. The mapping of bits from the
control words to the
irx_calendar
output signal is consistent with the mapping of bits from the
itx_calendar
input signal to the control words.
On the RX side, your application is responsible for mapping the calendar pages to the corresponding
channels, according to any interpretation agreed upon with the Interlaken link partner application in
sideband communication. On the TX side, your application is responsible for throttling the data it
transfers to the TX user data transfer interface, in response to the agreed upon interpretation of the
irx_calendar
bits.
Related Information
•
50G Interlaken IP Core In-Band Calendar Bits on Transmit Side
on page 4-12
•
50G Interlaken IP Core Receiver Side Example With Errors and In-Band Calendar Bits
on page 4-
17
Example of in-band calendar bits usage on the RX user data transfer interface.
4-18
In-Band Calendar Bits on the 50G Interlaken IP Core Receiver User Data Interface
UG-01140
2015.05.04
Altera Corporation
Functional Description