Altera SCFIFO - Manual (Page 20)

register. To ensure the
q
output is valid, sample the output only after the
rdempty
signal is
deasserted.
Related Information
Quartus II TimeQuest Timing Analyzer
Provides information about setting the timing constraint
Coding Example for Manual Instantiation
This section provides a Verilog HDL coding example to instantiate the DCFIFO IP core. It is not a
complete coding for you to compile, but it provides a guideline and some comments for the required
structure of the instantiation. You can use the same structure to instantiate other IP cores but only with
the ports and parameters that are applicable to the IP cores you instantiated.
Table 11: Verilog HDL Coding Example to Instantiate the DCFIFO IP Core
//module declaration
module dcfifo8x32 (aclr, data, …… ,wfull);
//Module's port declarations input aclr;
input [31:0] data;
.
.
output wrfull;
//Module’s data type declarations and assignments wire rdempty_w;
.
.
wire wrfull = wrfull_w; wire [31:0] q = q_w;
/*Instantiates dcfifo megafunction. Must declare all the ports available from the
megafunction and
define the connection to the module's ports.
Refer to the ports specification from the user guide for more information about the
megafunction's
ports*/
//syntax: dcfifo inst1 (
//syntax: .()
.wrclk (wrclk),
.rdclk (rdreq),
.
.
.wrusedw ()); //left the output open if it's not used
/*Start with the keyword “defparam”, defines the parameters and value assignments.
Refer to
parameters specifications from the user guide for more information about the megafunc-
tion's
parameters*/
defparam
//syntax: . = inst1.intended_device_family =
"Stratix III",
inst1.lpm_numwords = 8,
.
.
inst1.wrsync_delaypipe = 4;
endmodule
20 Coding Example for Manual Instantiation
UG-MFNALT_FIFO
2014.12.17
Altera Corporation SCFIFO and DCFIFO IP Cores User Guide
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