Altera SCFIFO User Manual
Page 13
Table 5: LE Implemented RAM Mode for SCFIFO and DCFIFO
Output Mode
Optimization Option
(10)
Output Latency (in number of clock cycles)
(11)
Normal
(12)
Speed
wrreq
/
rdreq
to
full
: 1
wrreq
to
empty
: 2
rdreq
to
empty
: 1
wrreq
/
rdreq
to
usedw[]
: 1
rdreq
to
q[]
: 1
Area
wrreq
/
rdreq
to
full
: 1
wrreq
/
rdreq
to
empty
: 1
wrreq
/
rdreq
to
usedw[]
: 1
rdreq
to
q[]
: 1
Show-ahead
(12)
Speed
wrreq
/
rdreq
to
full
: 1
wrreq
to
empty
: 3
rdreq
to
empty
: 1
wrreq
/
rdreq
to
usedw[]
: 1
wrreq
to
q[]
: 1
rdreq
to
q[]
: 1
Area
wrreq
/
rdreq
to
full
: 1
wrreq
to
empty
: 2
rdreq
to
empty
: 1
wrreq
/
rdreq
to
usedw[]
: 1
wrreq
to
q[]
: 1
rdreq
to
q[]
: 1
(10)
Speed optimization is equivalent to setting the
ADD_RAM_OUTPUT_REGISTER
parameter to
ON
. Setting the
parameter to
OFF
is equivalent to area optimization.
(11)
The information of the output latency is applicable for Stratix and Cyclone series only. It may not be
applicable for legacy devices such as the APEX
®
and FLEX
®
series.
(12)
For the Quartus II software versions earlier than 9.0, the normal output mode is called legacy output mode.
Normal output mode is equivalent to setting the
LPM_SHOWAHEAD
parameter to
OFF
. For Show-ahead mode,
the parameter is set to
ON
.
UG-MFNALT_FIFO
2014.12.17
SCFIFO and DCFIFO Output Status Flag and Latency
13
SCFIFO and DCFIFO IP Cores User Guide
Altera Corporation