Kontron VM162 - Manual (Page 77)

VM162/VM172 Chapter 4 Programming
July 19,1997 Page 4- 7 © PEP Modular Computers
Address List of Involved Registers
MBAR 0x3FF00 (CPU space!)
RSR 0xC0001009
SYPCR 0xC0001022
MCR 0xC0001000
PLLCR 0xC0001010
CDVCR 0xC0001014
CLKOCR 0xC000100C
PEPAR 0xC0001016
GMR 0xC0001040
AVR 0xC0001008
BR0 0xC0001050
OR0 0xC0001054
BR1 0xC0001060
OR1 0xC0001064
BR2 0xC0001070
OR2 0xC0001074
BR3 0xC0001080
OR3 0xC0001084
BR4 0xC0001090
OR4 0xC0001094
BR5 0xC00010A0
OR5 0xC00010A4
BR6 0xC00010B0
OR6 0xC00010B4
BR7 0xC00010C0
OR7 0xC00010C4
CICR 0xC0001540
SDCR 0xC000151E
VCSR 0xCD000005
BCSR 0xCD000007
4.3 Initializing the Cache
Before the system enables any cache present, they should be invalidated using:
cinva bc
Furthermore, the complete address range should not be cachable, as caching only makes sense on
DRAM and FLASH EPROM. Other areas should never be cached and must be switched to serialized in
order to prevent the MC68040/MC68060 from mixing up read and write cycles.
The easiest way of doing this is to make use of the DTT0 register, in the following way:
move.l #$807FE040,d1
movec d1,dtt0
The code above sets all addresses below $80000000 to cacheable and non-serialized, whereas all
addresses above are set to non-cacheable and serialized.