Cirrus Logic CS42L51 - Manual (Page 87)

DS679F1 87
CS42L51
PP1
Adjusted the minimum voltage specification in “Specified Operating Conditions” section on page 12 .
Adjusted Ambient Operating Temp. specification in “Absolute Maximum Ratings” section on page 12 .
Adjusted maximum “Analog In to PGA to ADC” THD+N performance specification in “Analog Input Characteris-
tics (Commercial - CNZ)” on page 13 .
Added Offset Error specification to “Analog Input Characteristics (Commercial - CNZ)” on page 13 and “Analog
Input Characteristics (Automotive - DNZ)” on page 14 .
Corrected Interchannel Gain Mismatch specification in “Analog Input Characteristics (Commercial - CNZ)” on
page 13 and “Analog Input Characteristics (Automotive - DNZ)” on page 14 .
Adjusted ADC full scale input voltage specification in “Analog Input Characteristics (Commercial - CNZ)” on
page 13 and “Analog Input Characteristics (Automotive - DNZ)” on page 14 .
Corrected Group Delay characteristic in table in section “ADC Digital Filter Characteristics” on page 15 .
Adjusted maximum “R
L
= 10k Ω” THD+N performance specification in “Analog Output Characteristics (Commer-
cial - CNZ)” on page 16 and “Analog Output Characteristics (Automotive - DNZ)” on page 17 .
Corrected Group Delay characteristic in table in section “Combined DAC Interpolation & on-Chip Analog FIlter
Response” on page 20 .
Adjusted timing specifications t
d(MSB)
from 40 ns to 52 ns and t
s(SDO-SK)
from 30 ns to 20 ns in table in section
“Switching Specifications - Serial Port” on page 20 .
Adjusted I²C timing specification t
ack
from 1000 ns to 3450 ns in table in section “” on page 21 .
Adjusted High-Level Input Voltage specifications V
IH
from 0.65VL to 0.68VL and V
IL
from 0.35VL to 0.32VL in
table in section “Digital Interface Specifications & Characteristics” on page 24 .
Adjusted the +20 dB Digital Boost block before the ALC feedback path in Figure 8 on page 28 .
Modified ALC Recommended Settings in section “Automatic Level Control (ALC)” on page 32 .
Modified step 2 of the “Recommended Power-Down Sequence” on page 42 .
Corrected default values for ALC and Limiter Release Rates shown in “Register Quick Reference” on page 46 .
Corrected default value for the DAC_SZC bits and Added AMUTE bit and description in “DAC Control (Address
09h)” on page 58 .
Added section “Headphone Amplifier Efficiency” on page 77 .
Corrected ADC Filter Response shown in Figures 34 , 35 , 36 , and 37 on page 82 .
Corrected ADC_SNGVOL description in “MIC Control (Address 05h)” on page 53 .
F1 Final Release
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