Cirrus Logic CS42L51 - Manual (Page 50)

50 DS679F1
CS42L51
Power Down PGA X (PDN_PGAX)
Default: 0
0 - Disable
1 - Enable
Function:
PGA channel x will either enter a power-down or muted state when this bit is enabled. See Power Control
1 (Address 02h) on page 49 above.
This bit is used in conjunction with AINx_MUX bits to determine the analog input path to the ADC. Refer to
“ADCX Input Select Bits (AINX_MUX[1:0])” on page 56 for the required settings.
Power Down ADC X (PDN_ADCX)
Default: 0
0 - Disable
1 - Enable
Function:
ADC channel x will either enter a power-down or muted state when this bit is enabled. See Note 1 on page
49 .
Power Down (PDN)
Default: 0
0 - Disable
1 - Enable
Function:
The entire CODEC will enter a low-power state when this function is enabled. The contents of the control
port registers are retained in this mode.
6.3 MIC Power Control & Speed Control (Address 03h)
Auto-Detect Speed Mode (AUTO)
Default: 1
0 - Disable
1 - Enable
Function:
Enables the auto-detect circuitry for detecting the speed mode of the CODEC when operating as a slave.
When AUTO is enabled, the MCLK/LRCK ratio must be implemented according to
Table 3 on page 39 . The
SPEED[1:0] bits are ignored when this bit is enabled. Speed is determined by the MCLK/LRCK ratio.
7 6 5 4 3 2 1 0
AUTO SPEED1 SPEED0 3-ST_SP PDN_MICB PDN_MICA PDN_MICBIAS MCLKDIV2