Figure 4. serial audio interface slave mode timing, Note 14), Note 15) – Cirrus Logic CS42L51 User Manual
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CS42L51
14. After powering up the CS42L51, RESET should be held low after the power supplies and clocks are
settled.
“Example System Clock Frequencies” on page 79
for typical MCLK frequencies.
16. See
17.
18. “MCLK” refers to the external master clock applied.
Master Mode
Output Sample Rate (LRCK)
All Speed Modes
F
s
-
Hz
LRCK Duty Cycle
45
55
%
SCLK Frequency
1/t
P
-
64•F
s
Hz
SCLK Duty Cycle
45
55
%
LRCK Edge to SDOUT MSB Output Delay
t
d(MSB)
-
52
ns
SDOUT Setup Time Before SCLK Rising Edge
t
s(SDO-SK)
20
-
ns
SDOUT Hold Time After SCLK Rising Edge
t
h(SK-SDO)
30
-
ns
SDIN Setup Time Before SCLK Rising Edge
t
s(SD-SK)
20
-
ns
SDIN Hold Time After SCLK Rising Edge
t
h
20
-
ns
Parameters
Symbol Min
Max
Units
MCLK
128
-----------------
t
h(SK-SDO)
//
//
//
//
//
//
//
//
t
s(SD-SK)
MSB
MSB
MSB-1
MSB-1
LRCK
SCLK
SDOUT
SDIN
t
d(MSB)
t
s(LK-SK)
t
P
t
h
t
s(SDO-SK)
Figure 4. Serial Audio Interface Slave Mode Timing
t
h(SK-SDO)
//
//
//
//
//
//
//
//
t
s(SD-SK)
MSB
MSB
MSB-1
MSB-1
LRCK
SCLK
SDOUT
SDIN
t
d(MSB)
t
P
t
h
t
s(SDO-SK)
Figure 5. Serial Audio Interface Master Mode Timing