Register quick reference – Cirrus Logic CS42L51 User Manual
Page 46
46
DS679F1
CS42L51
5. REGISTER QUICK REFERENCE
Software mode register defaults are as shown. “Reserved” registers must maintain their default state.
Addr
Function
7
6
5
4
3
2
1
0
01h
ID
Chip_ID4
Chip_ID3
Chip_ID2
Chip_ID1
Chip_ID0
Rev_ID2
Rev_ID1
Rev_ID0
default
1
1
0
1
1
0
0
1
02h
Power Ctl. 1
Reserved
PDN_DACB PDN_DACA dPDN_PGAB PDN_PGAA
PDN_ADCB
PDN_ADCA
PDN
default
0
0
0
0
0
0
0
0
03h
Speed Ctl. &
Power Ctl. 2
AUTO
SPEED1
SPEED0
3-ST_SP
PDN_MICB
PDN_MICA
PDN_
MICBIAS
MCLKDIV2
default
1
0
1
0
1
1
1
0
04h
Interface Ctl.
SDOUT->SDIN
M/S
DAC_DIF2
DAC_DIF1
DAC_DIF0
ADC_I²S/LJ
DIGMIX
MICMIX
default
0
0
0
0
0
0
0
0
05h
MIC Control
& Misc.
ADC_SNGVOL
ADCB_
DBOOST
ADCA_
DBOOST
MICBIAS_
SEL
MICBIAS_
LVL1
MICBIAS_
LVL0
MICB_
BOOST
MICA_
BOOST
default
0
0
0
0
0
0
0
0
06h
ADC Control
ADCB_HPF
EN
ADCB_HP
FRZ
ADCA_HPF
EN
ADCA_HP
FRZ
SOFTB
ZCROSSB
SOFTA
ZCROSSA
default
1
0
1
0
0
0
0
0
07h
ADC Input
Select
, Invert, Mute
AINB_MUX1
AINB_MUX
0
AINA_MUX1 AINA_MUX0
INV_ADCB
INV_ADCA
ADCB_
MUTE
ADCA_
MUTE
default
0
0
0
0
0
0
0
0
08h
DAC Output
Control
HP_GAIN2
HP_GAIN1
HP_GAIN0
DAC_SNG
VOL
INV_PCMB
INV_PCMA
DACB_
MUTE
DACA_
MUTE
default
0
1
1
0
0
0
0
0
09h
DAC Control
DATA_SEL1
DATA_SEL0
FREEZE
Reserved
DEEMPH
AMUTE
DAC_SZC1
DAC_SZC0
default
0
0
0
0
0
1
1
0
0Ah
ALCA SZC &
PGAA Vol-
ume
ALCA_SR
DIS
ALCA_ZC
DIS
Reserved
PGAA
VOL4
PGAA
VOL3
PGAA
VOL2
PGAA
VOL1
PGAA
VOL0
default
0
0
0
0
0
0
0
0
0Bh
ALCB SZC &
PGAB Vol-
ume
ALCB_SR
DIS
ALCB_ZC
DIS
Reserved
PGAB
VOL4
PGAB
VOL3
PGAB
VOL2
PGAB
VOL1
PGAB
VOL0
default
0
0
0
0
0
0
0
0
0Ch
ADCA Atten-
uator
ADCA_
ATT7
ADCA_
ATT6
ADCA_
ATT5
ADCA_
ATT4
ADCA_
ATT3
ADCA_
ATT2
ADCA_
ATT1
ADCA_
ATT0
default
0
0
0
0
0
0
0
0
0Dh
ADCB Atten-
uator
ADCB_
ATT7
ADCB_
ATT6
ADCB_
ATT5
ADCB_
ATT4
ADCB_
ATT3
ADCB_
ATT2
ADCB_
ATT1
ADCB_
ATT0