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Table 6-28, Isa legacy i/o register summary – AMD Geode SC3200 User Manual

Page 186

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186

AMD Geode™ SC3200 Processor Data Book

Core Logic Module - Register Summary

32581C

Table 6-28. ISA Legacy I/O Register Summary

I/O Port

Type

Name

Reference

DMA Channel Control Registers (Table 6-43)

000h

R/W

DMA Channel 0 Address Register

Page 295

001h

R/W

DMA Channel 0 Transfer Count Register

Page 295

002h

R/W

DMA Channel 1 Address Register

Page 295

003h

R/W

DMA Channel 1 Transfer Count Register

Page 295

004h

R/W

DMA Channel 2 Address Register

Page 295

005h

R/W

DMA Channel 2 Transfer Count Register

Page 295

006h

R/W

DMA Channel 3 Address Register

Page 295

007h

R/W

DMA Channel 3 Transfer Count Register

Page 295

008h

Read

DMA Status Register, Channels 3:0

Page 295

Write

DMA Command Register, Channels 3:0

Page 296

009h

WO

Software DMA Request Register, Channels 3:0

Page 296

00Ah

W

DMA Channel Mask Register, Channels 3:0

Page 296

00Bh

WO

DMA Channel Mode Register, Channels 3:0

Page 297

00Ch

WO

DMA Clear Byte Pointer Command, Channels 3:0

Page 297

00Dh

WO

DMA Master Clear Command, Channels 3:0

Page 297

00Eh

WO

DMA Clear Mask Register Command, Channels 3:0

Page 297

00Fh

WO

DMA Write Mask Register Command, Channels 3:0

Page 297

0C0h

R/W

DMA Channel 4 Address Register (Not used)

Page 297

0C2h

R/W

DMA Channel 4 Transfer Count Register (Not Used)

Page 297

0C4h

R/W

DMA Channel 5 Address Register

Page 297

0C6h

R/W

DMA Channel 5 Transfer Count Register

Page 297

0C8h

R/W

DMA Channel 6 Address Register

Page 297

0CAh

R/W

DMA Channel 6 Transfer Count Register

Page 297

0CCh

R/W

DMA Channel 7 Address Register

Page 297

0CEh

R/W

DMA Channel 7 Transfer Count Register

Page 297

0D0h

Read

DMA Status Register, Channels 7:4

Page 298

Write

DMA Command Register, Channels 7:4

Page 298

0D2h

WO

Software DMA Request Register, Channels 7:4

Page 299

0D4h

W

DMA Channel Mask Register, Channels 7:4

Page 299

0D6h

WO

DMA Channel Mode Register, Channels 7:4

Page 299

0D8h

WO

DMA Clear Byte Pointer Command, Channels 7:4

Page 299

0DAh

WO

DMA Master Clear Command, Channels 7:4

Page 299

0DCh

WO

DMA Clear Mask Register Command, Channels 7:4

Page 299

0DEh

WO

DMA Write Mask Register Command, Channels 7:4

Page 300

DMA Page Registers (Table 6-44)

081h

R/W

DMA Channel 2 Low Page Register

Page 300

082h

R/W

DMA Channel 3 Low Page Register

Page 300

083h

R/W

DMA Channel 1 Low Page Register

Page 300

087h

R/W

DMA Channel 0 Low Page Register

Page 300

089h

R/W

DMA Channel 6 Low Page Register

Page 300

08Ah

R/W

DMA Channel 7 Low Page Register

Page 300

08Bh

R/W

DMA Channel 5 Low Page Register

Page 300

08Fh

R/W

Sub-ISA Refresh Low Page Register

Page 300

481h

R/W

DMA Channel 2 High Page Register

Page 300

482h

R/W

DMA Channel 3 High Page Register

Page 300

483h

R/W

DMA Channel 1 High Page Register

Page 300