IEI Integration PCIE-Q350 v1.30 - Manual (Page 44)

PCIE-Q350 PICMG 1.3 CPU Card
Page 24
Native IDE enabled operating system: Two controllers enable all six ports
on the bus. Controller 1 supports Port 0, Port 1, Port 2 and Port 3. Controller 2
supports Ports 4 and Port 5.
Legacy operating system is used: One controller is enabled and only
supports Port 0, Port 1, Port 2 and Port 3.
AHCI or RAID mode: One controller supports all six ports including, Port 0,
Port 1, Port 2, Port 3, Port 4 and Port 5.
In the AHCI or RAID mode, 3.0 Gbps data transfer speeds are supported. The SATA drive
connectors are shown in Figure 2-10.
Figure 2-10: SATA Drive Connectors
2.5.9 Intel
®
ICH9DO Serial Peripheral Interface (SPI) BIOS
The 4-pin SPI is connected to an SPI BIOS chip. A licensed copy of AMI BIOS is
preinstalled on the SPI BIOS chip. A master-slave protocol is used for communication on
the SPI bus. The slave is connected to the Intel® ICH9DO Southbridge and is
implemented as a tri-state bus.
2.5.10 Intel
®
ICH9DO USB Controller
2.5.10.1 Intel
®
ICH9DO USB Controller Overview
The ICH9DO comprises six full/low speed USB controllers that support the standard
Universal Host Controller Interface (UHCI) Revision 1.1. Each controller supports two
USB devices ensuring up to twelve USB 1.1 devices can be connected to the PCIE-Q350.