Rainbow Electronics T89C5121 - Manual (Page 81)

81
A/T8xC5121
4164G–SCR–07/06
Serial I/O Port
The serial I/O port is entirely compatible with the serial I/O port in the 80C52.
It provides both synchronous and asynchronous communication modes. It operates as
an Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex
modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simul-
taneously and at different baud rates.
Serial I/O port includes the following enhancements:
• Framing error detection and Automatic Address Recognition
• Internal Baud Rate Generator
Figure 32. Serial I/O UART Port Block Diagram
Framing Error Detection Framing bit error detection is provided for the three asynchronous modes. To enable the
framing bit error detection feature, set SMOD0 bit in PCON register.
Figure 33. Framing Error Block Diagram
When this feature is enabled, the receiver checks each incoming data frame for a valid
stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous
transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in
SCON register bit is set.
Software may examine FE bit after each reception to check for data errors. Once set,
only software or a reset clear FE bit. Subsequently received frames with valid stop bits
cannot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the last
data bit (See Figure 34 and Figure 35).
Write SBUF
RI TI
Transmitter
SBUF
Receiver
IB Bus
Mode 0 Transmit
Receive
Shift register
Load SBUF
Read SBUF
Interrupt Request
Serial Port
TXD
RXD
SBUF
RI TI RB8 TB8 REN SM2 SM1 SM0/FE
IDL PD GF0 GF1 POF - SMOD0 SMOD1
To UART framing error control
SM0 to UART mode control
Set FE bit if stop bit is 0 (framing error)