Rainbow Electronics T89C5121 - Manual (Page 67)

67
A/T8xC5121
4164G–SCR–07/06
}
void generate_crc_in_frame(void)
{
checksum_tx=(Uint16) FFFFh; /* init of the crc variable */
/* loop which compute for each byte (data_byte) to load */
checksum_tx=compute_crc((Uint16)data_byte^checksum_tx)^(checksum_tx>>8);
/* end of loop */
checksum=~checksum_tx; /* inverts the checksum, so the check will calculate
the CRC of all the datas and */
/* will find a constant value = F0B8
which is the CRC_REF const. of the Bootloader */
write_frame(LOW_BYTE(checksum)); /* writes the LOW_BYTE of the CRC first */
write_frame(HIGH_BYTE(checksum)); /* writes the HIGH_BYTE */
}
***************************************************************************************************
Table 47. Synthesis of Transfer Protection Mechanisms
Notes: 1. The transfer of SSB Byte is also secured by CRC as the CRC is computed on all the
16K data.
2. If a Bad transfer has occurred in the Internal EEPROM (CRC is bad), as the CRC
check is finally done at the end of CRAM programming, application program will NOT
be executed after any Reset.
Read/Write Protection
Lock Byte In order to protect the content of the internal EEPROM, a Software Security Byte (SSB)
defines two security levels:
• level 0: SSB = 0xFF: Write and Read are allowed
• level 1: SSB = 0xFE: Write is disabled
• level 2: SSB = 0xFC: Write and Read are disabled
This SSB Byte is located at address 3FFDh.
When the level 2 is set, the command to set level 1 is disabled. The security levels can
only be increased.
Source Target Check
MCU CRAM
CRC computed during CRAM Write operation: if error an error code is applied
on P3.7 and Code execution by LJMP000 is not done.
Intern. EEP MCU This Read operation is secured by the Write sequence described above
MCU Intern. EEP
Same protection as in first row above because CRAM is written in sequence
after each page programming of EEP
Ext. EEP MCU Same as above as data are transferred to EEP INT and then to CRAM