Rainbow Electronics DS28DG02 - Manual (Page 25)

DS28DG02: 2kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog
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is 1 AND the number if bits sent by the master is a multiple of 8 (i.e., full byte only), the write cycle (transfer from
the buffer to EEPROM) begins with the positive edge of CSZ. The duration of the write cycle is t
PROG
, during which
the RDYZ bit of the SPI Status register reads 1. After the write cycle is completed, the WEN bit is cleared. If the
target memory is write-protected OR WEN was not set to 1 before issuing the WRITE instruction OR the number of
data bits that followed the address byte was not a multiple of 8, the positive edge on CSZ does not start a write
cycle and the WEN bit is not cleared.
The six EEPROM registers, together with the reserved addresses, form another memory segment. Write access to
this segment is essentially the same as for the user memory with the following differences: The data sent by the
master that normally would apply to the first 10 bytes of the segment is discarded. A write cycle is initiated only if
the WEN bit of the SPI Status register is 1 AND the number if bits sent by the master is a multiple of 8 (i.e., full byte
only) AND at least one EEPROM byte is to be updated. If WEN was not set to 1 before issuing the WRITE
instruction OR the number of data bits that followed the address byte was not a multiple of 8 OR all data bytes sent
by the master applied to the nonwriteable addresses, the positive edge on CSZ does not start a write cycle and the
WEN bit is not cleared.
Write access to the SRAM, PIO, and NV SRAM does not involve a write buffer. If the WEN bit is 1 AND RPROT =
0 AND the target address is writeable, a data byte that follows the target address becomes effective as soon as its
transmission is completed. The address pointer increments after each data byte, directing subsequent bytes to the
next higher addresses. If the target address is read-only, data for that address is discarded. After address 135h is
updated, the address pointer wraps around to 120h. The master may continue sending data bytes indefinitely. The
write access ends with the positive edge on CSZ. The last byte, if incomplete, is ignored. The WEN bit is cleared
only if at least one byte was written to a writeable address. If RPROT = 1 the memory is not updated and the WEN
bit remains set.
The RTC should be updated starting with the Seconds register. If the starting target address
specified after the instruction code points to the PIO Output State registers (address 120h or 121h) and the PIO
output mode OTM is 0 (low current) the address pointer toggles between 120h and 121h after the data byte is
transmitted. This allows fast PIO updates, e.g., for generating data patterns. For OTM = 1 (high-current) the
address pointer increments to the next higher address. For a PIO-update timing diagram and the differences
between low-current and high-current mode, see the PIO Read/Write Access section.
Upon receiving a write instruction with an address targeting the read-only memory or non-existing memory, all data
is discarded and no write cycle or data update takes place. Since the write access is not successful, the WEN bit in
the SPI Status register is not cleared.
As a precondition for a successful WRITE instruction, the WEN bit in the SPI Status register must be 1. The WEN
bit is set through the WREN instruction, which must be completed before the WRITE instruction. The WRITE timing
diagram for both SPI communication modes is shown in Figure 18 (single-byte write) and Figure 19 (multiple-byte
write). The programming time t
PROG
applies only to EEPROM writes. For writes to the SRAM, PIO, and NV SRAM in
SPI mode (0,0) the actual transfer to the target memory takes place on the falling SCK edge of the LS-bit of a data
byte. In SPI mode (1,1) the actual transfer to the target memory also takes place on the falling SCK edge of the LS-
bit of a data byte, except for the last byte, which is transferred on the rising edge of CSZ.