Rainbow Electronics AT45DB642 User Manual
Megabit 2.7-volt only dual-interface dataflash, Features, Description
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1
Features
•
Single 2.7V - 3.6V Supply
•
Dual-interface Architecture
– Dedicated Serial Interface (SPI Modes 0 and 3 Compatible)
– Dedicated Parallel I/O Interface (Optional Use)
•
Page Program Operation
– Single Cycle Reprogram (Erase and Program)
– 8192 Pages (1056 Bytes/Page) Main Memory
•
Supports Page and Block Erase Operations
•
Two 1056-byte SRAM Data Buffers – Allows Receiving of Data
while Reprogramming the Flash Array
•
Continuous Read Capability through Entire Array
– Ideal for Code Shadowing Applications
•
Low-power Dissipation
– 4 mA Active Read Current Typical
– 2 µA CMOS Standby Current Typical
•
20 MHz Maximum Clock Frequency – Serial Interface
•
5 MHz Maximum Clock Frequency – Parallel Interface
•
Hardware Data Protection
•
Commercial and Industrial Temperature Ranges
Description
The AT45DB642 is a 2.7-volt only, dual-interface Flash memory ideally suited for a
wide variety of digital voice-, image-, program code- and data-storage applications. The
dual-interface of the AT45DB642 allows a dedicated serial interface to be connected to a
DSP and a dedicated parallel interface to be connected to a microcontroller or vice versa.
64-megabit
2.7-volt Only
Dual-interface
DataFlash
®
AT45DB642
Pin Configurations
Pin Name
Function
CS
Chip Select
SCK/CLK
Serial Clock/Clock
SI
Serial Input
SO
Serial Output
I/O7 - I/O0
Parallel Input/Output
WP
Hardware Page Write Protect Pin
RESET
Chip Reset
RDY/BUSY
Ready/Busy
SER/PAR
Serial/Parallel Interface Control
DataFlash Card
Note:
1. See AT45DCB008 Datasheet.
7 6 5 4 3 2 1
TSOP Top View
Type 1
Note:
*Optional Use – See pin description
text for connection information.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
NC
NC
RDY/BUSY
RESET
WP
NC
NC
NC
VCC
GND
NC
NC
NC
NC
CS
SCK/CLK
SI*
SO*
NC
NC
NC
NC
NC
NC
NC
I/O7*
I/O6*
I/O5*
I/O4*
VCCP*
GNDP*
I/O3*
I/O2*
I/O1*
I/O0*
SER/PAR*
NC
NC
NC
NC
Rev. 1638F–DFLSH–09/02
Document Outline
- Pin Configurations
- Features
- Description
- Block Diagram
- Memory Array
- Memory Architecture Diagram
- Device Operation
- Status Register Format
- Block Erase Addressing
- Power-on/Reset State
- System Considerations
- Absolute Maximum Ratings*
- DC and AC Operating Range
- DC Characteristics
- AC Characteristics – Serial/Parallel Interface
- AC Characteristics – Serial Interface
- Test Waveforms and Measurement Levels
- Output Test Load
- AC Waveforms
- Write Operations
- Read Operations
- Detailed Bit-level Read Timing – Inactive Clock Polarity Low
- Detailed Bit-level Read Timing – Inactive Clock Polarity Low (Continued)
- Detailed Bit-level Read Timing – Inactive Clock Polarity High
- Detailed Bit-level Read Timing – Inactive Clock Polarity High (Continued)
- Detailed Bit-level Read Timing – SPI Mode 0
- Detailed Bit-level Read Timing – SPI Mode 0 (Continued)
- Detailed Bit-level Read Timing – SPI Mode 3
- Detailed Bit-level Read Timing – SPI Mode 3 (Continued)
- Detailed Parallel Read Timing – SPI Mode 0
- Detailed Parallel Timing – SPI Mode 0 (Continued)
- Detailed Parallel Read Timing – SPI Mode 3
- Detailed Parallel Read Timing – SPI Mode 3 (Continued)
- Sector Addressing
- Ordering Information
- Packaging Information