Rainbow Electronics DS28DG02 - Manual (Page 14)

DS28DG02: 2kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog
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BIT DESCRIPTION BIT(S) DEFINITION
RST: Reset Flag b0
RSTZ pin activity indicator; set whenever there is a pulse at RSTZ;
cleared by writing to the Alarm and Status register.
V
CC
ramp up: 1; V
BAT
attach: 0
WDA: Watchdog Alarm b1
Watchdog Alarm indicator; set whenever the watchdog is enabled AND
the watchdog timer expires; cleared by writing to the Alarm and Status
register.
V
CC
ramp up: 0; V
BAT
attach: 0
CLKA: Clock Alarm b2
RTC /Calendar Alarm indicator; set whenever the clock alarm is enabled
AND RTC and RTC Alarm register match; cleared by writing to the
Alarm and Status register.
V
CC
ramp up: 0; V
BAT
attach: 0
BOR: Battery-On Reset
Flag
b3
Battery attach indicator; set whenever the voltage at V
BAT
ramps up
above V
BATmin
; cleared by writing to the Alarm and Status register.
V
CC
ramp up: not affected; V
BAT
attach: 1
POR: Power-On Reset
Flag
b4
Power-On Reset indicator; set whenever the voltage at V
CC
ramps up
above V
CCmin
; cleared by writing to the Alarm and Status register.
V
CC
ramp up: 1; V
BAT
attach: 0
WPZV: Hardware Write
Protect Value
b5
WPZ pin state readout; reports the logic state at the WPZ pin;
V
CC
ramp up: WPZ pin state; V
BAT
attach: not affected.
BATA: Battery Alarm b6
Low Battery indicator; set whenever the battery alarm is enabled AND if,
during a battery test, V
BAT
is below the selected V
BAT
trip point; cleared
by writing to the Alarm and Status register.
V
CC
ramp up: battery test if BME = 1; V
BAT
attach: 0
Figure 5. ALMZ, WDOZ, and RSTZ Generation
BME, CAE, WDE, WDOS are defined in the Control/Setup register.
BATA, CLKA, WDA are alarm signals readable through the Alarm/Status register.
VCLA is the alarm output of the V
CC
monitor.
WDE
WDA
WDOS
VCLA
Debounce
BME
BATA
CAE
CLKA
WDOZ
RSTZ
ALMZ