Xilinx 1000BASE-X - Manual (Page 66)

66 www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
UG155 March 24, 2008
Chapter 5: Using the Client-side GMII Data Path R
GMII Receiver Logic
Figure 5-18 illustrates an external GMII receiver created in a Virtex-II family device. The
signal names and logic shown in the figure exactly match those delivered with the example
design when the GMII is selected. If other families are selected, equivalent primitives and
logic specific to that family is automatically used in the example design.
Figure 5-18 also shows that the output receiver signals are registered in device IOBs before
driving them to the device pads. The logic required to forward the receiver GMII clock is
also shown. This uses an IOB output Double-Data-Rate (DDR) register so that the clock
signal produced incurs exactly the same delay as the data and control signals. This clock
signal, gmii_rx_clk, is inverted so that the rising edge of gmii_rx_clk occurs in the
center of the data valid window, which maximizes setup and hold times across the
interface. All receiver logic is synchronous to a single clock domain.
The clock name varies depending on the CORE Generator options. When used with the
RocketIO transceiver, the clock name is userclk2; when used with the TBI, the clock
name is gtx_clk. For more information on clocking, see Chapters 6, 7 and 8.