Table 9-29, Register 0: sgmii control – Xilinx 1000BASE-X User Manual
Page 145
Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
145
UG155 March 24, 2008
Management Registers
R
SGMII Standard without the Optional Auto-Negotiation
The Registers provided for SGMII operation in this core are adaptations of those defined in
IEEE 802.3 clauses 37 and 22. In an SGMII implementation, two different types of links
exist. They are the SGMII link between the MAC and PHY (SGMII link) and the link across
the Ethernet Medium itself (Medium). See
. Information about the state of the
SGMII link is available in registers that follow.
The state of the link across the Ethernet Medium itself is not directly available when SGMII
Auto-Negotiation is not present. For this reason, the status of the link and the results of the
PHYs Auto-Negotiation (for example, Speed and Duplex mode) must be obtained directly
from the management interface of connected PHY module. Registers at undefined
addresses are read-only and return 0s.
Register 0: SGMII Control
Table 9-29:
MDIO Registers for 1000BASE-X with Auto-Negotiation
Register Address
Register Name
0
SGMII Control Register
1
SGMII Status Register
2,3
PHY Identifier
4
SGMII Auto-Negotiation Advertisement Register
15
SGMII Extended Status Register
MDIO Register 0: SGMII Control
RESET
LOOPBA
CK
A
U
T
O-NEG ENABLE
REST
AR
T A
U
T
O-NEG
RESER
VED
PO
WER DO
WN
SPEED
SPEED
15 14 13 12 11 10
7
6
5
0
Reg 0
ISOLA
TE
9
8
DUPLEX MODE
COLLISION TEST
4
UNIDIRECTIONAL ENABLE