Xilinx 1000BASE-X - Manual (Page 159)

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com 159
UG155 March 24, 2008
Operation of the Core R
replace the link_timer_value[8:0] port that is used when the core is generated for a
single standard.
•
link_timer_basex[8:0] The value placed on this port is sampled at the
beginning of the Auto-Negotiation cycle by the Link Timer when the core is set to
perform the 1000BASE-X standard.
•
link_timer_sgmii[8:0] The value placed on this port is sampled at the
beginning of the Auto-Negotiation cycle by the Link Timer when the core is set to
perform the SGMII standard.
Both ports follow the same rules that are described in “Setting the Configurable Link
Timer,” page 156 .