Xilinx 1000BASE-X - Manual (Page 47)

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com 47
UG155 March 24, 2008
Design Overview R
1000BASE-X Standard with TBI Example Design
Figure 4-2 illustrates the example design in 1000BASE-X mode using a TBI. As illustrated,
the example is split between two hierarchical layers. The block level is designed so that it
can be instantiated directly into customer designs and performs the following functions:
•
Instantiates the core from HDL
•
Connects the physical-side interface of the core to device IOBs, creating an external
TBI. See
Chapter 6, “The Ten-Bit Interface.”
The top level of the example design creates a specific example that can be simulated,
synthesized, implemented, and if required, placed on a suitable board and demonstrated
in hardware. The top level of the example design performs the following functions:
•
Instantiates the block level from HDL
•
Derives the clock management logic for the core
•
Implements an external GMII
Figure 4-2: Example Design 1000BASE-X Standard Using TBI
Ethernet
1000BASE-X
PCS/PMA
Core
GMII
IOBs
Out
TBI
IOBs
Out
IOBs
In
(DDR)
component_name_example_design
component_name_block
Tx
Elastic
Buffer
Clock
Management
Logic
Connect to
Client MAC
TBI
(Connect to
SERDES)
IOBs
In