Xilinx 1000BASE-X - Manual (Page 131)

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com 131
UG155 March 24, 2008
Management Registers R
Register 1: Status Register
0.9 Restart Auto-
Negotiation Ignore this bit because Auto-Negotiation
is not included. read/ write 0
0.8 Duplex Mode Always returns a ‘1’ for this bit to signal
Full-Duplex Mode. returns 1 1
0.7 Collision Test Always returns a ‘0’ for this bit to disable
COL test. returns 0 0
0.6 Speed
Selection(MS
B) Always returns a ‘1’ for this bit. Together
with bit 0.13, speed selection of 1000
Mbps is identified returns 1 1
0.5 Unidirectiona
l Enable Ignore this bit because Auto-Negotiation
is not included. read/ write 0
0.4:0 Reserved Always return 0s , writes ignored. returns 0s 00000
Table 9-14: Control Register (Register 0) (Continued)
Bit(s) Name Description Attributes
Default
Value
MDIO Register 1: Status Register
Table 9-15: Status Register (Register 1)
Bit(s) Name Description Attributes
Default
Value
1.15 100BASE-T4 Always returns a ‘0’ for this bit since
100BASE-T4 is not supported returns 0 0
1.14 100BASE-X Full
Duplex Always returns a ‘0’ for this bit since
100BASE-X Full Duplex is not supported returns 0 0
1.13 100BASE-X Half
Duplex Always returns a ‘0’ for this bit since
100BASE-X Half Duplex is not supported returns 0 0
1.12 10 Mbps Full Duplex Always returns a ‘0’ for this bit since 10
Mbps Full Duplex is not supported returns 0 0
1.11 10 Mbps Half Duplex Always returns a ‘0’ for this bit since 10
Mbps Half Duplex is not supported returns 0 0
100BASE-T4 100BASE-X FULL DUPLEX 10Mb/s FULL DUPLEX 100BASE-T2 HALF DUPLEX LINK ST
A
TUS
10Mb/s HALF DUPLEX 100BASE-X HALF DUPLEX MF PREAMBLE SUPPRESSION
15 14 13 12 11 10 7 6 5 0
Reg 1
100BASE-T2 FULL DUPLEX
9 8
EXTENDED ST
A
T
US
UNIDIRECTIONAL ANILITY
4
A
U
T
O-NEG COMPLETE
3 2 1
REMO
TE F
A
UL
T
A
U
T
O-NEG ABILITY
J
ABBER DETECT
EXTENDED CAP
ABILITY