Xilinx 1000BASE-X - Manual (Page 201)

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com 201
UG155 March 24, 2008
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Chapter 15
Implementing the Design
This chapter describes how to simulate and implement your design containing the
Ethernet 1000BASE-X PCS/PMA or SGMII core.
Pre-implementation Simulation
A functional model of the Ethernet 1000BASE-X PCS/PMA or SGMII core netlist is
generated by the CORE Generator to allow simulation of the core in the design-phase of
the project.
Using the Simulation Model
For information about setting up your simulator to use the pre-implemented model, please
consult the Xilinx Synthesis and Verification Design Guide, included in your Xilinx software
installation.
The model is provided in the CORE Generator project directory.
VHDL Design Entry
.vhd
Verilog Design Entry
.v
This model can be compiled along with the user’s code to simulate the overall system.
Synthesis
XST - VHDL
In the CORE Generator project directory, there is a < component_name >.vho file that is a
component and instantiation template for the core. Use this to help instance the Ethernet
1000BASE-X PCS/PMA or SGMII core into your VHDL source.
After the entire design is complete, create the following:
•
An XST project file top_level_module_name .prj listing all the user source code
files
•
An XST script file top_level_module_name .scr containing your required
synthesis options.
To synthesize the design, run
$ xst -ifn top_level_module_name.scr