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26 receive buffer count 0 register (rbufcnt0), Rbufcnt0), Descriptions – Texas Instruments TMS320DM357 User Manual

Page 99: Section 4.25, Section 4.26

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4.25 Receive CPPI Interrupt Enable Clear Register (RCPPIIENCLRR)

4.26 Receive Buffer Count 0 Register (RBUFCNT0)

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Registers

The Receive CPPI Interrupt Enable Clear Register (RCPPIIENCLRR) is shown in

Figure 40

and described

in

Table 41

.

Figure 40. Receive CPPI Interrupt Enable Clear Register (RCPPIIENCLRR)

31

16

Reserved

R-0

15

4

3

0

Reserved

COMP_PENDING_INTR_EN

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 41. Receive CPPI Interrupt Enable Clear Register (RCPPIIENCLRR) Field Descriptions

Bit

Field

Value

Description

31-4

Reserved

0

Reserved

3-0

COMP_PENDING_INTR_EN

0-Fh

Receive CPPI Interrupt Enables

These are active high interrupt enables corresponding to the Receive CPPI
Completion Pending status bits. Writing a 1 to any of the bits in the Receive CPPI
Interrupt Enable Clear Register will result in clearing of the corresponding bit in the
Receive CPPI Interrupt Enable Register.

The Receive Buffer Count 0 Register (RBUFCNT0) is shown in

Figure 41

and described in

Table 42

.

Figure 41. Receive Buffer Count 0 Register (RBUFCNT0)

31

16

Reserved

R-0

15

0

BUFCNT

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 42. Receive Buffer Count 0 Register (RBUFCNT0) Field Descriptions

Bit

Field

Value

Description

31-16

Reserved

0

Reserved

15-0

BUFCNT

0-FFFFh

Receive CPPI Buffer Count

The current count of CPPI buffers in Receive channel 0 queue. Writes add to current value (not
overwrite). The DMA requires a minimum of 3 RX buffers to operate.

SPRUGH3 – November 2008

Universal Serial Bus (USB) Controller

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