Transactions – Texas Instruments TMS320DM357 User Manual
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USB Controller Host and Peripheral Modes Operation
3.1.4.2.1
Setup
In configuring an Rx endpoint for Isochronous OUT transactions, the RXMAXP register must be written
with the maximum packet size (in bytes) for the endpoint. This value should be the same as the
wMaxPacketSize field of the Standard Endpoint Descriptor for the endpoint. In addition, the relevant
interrupt enable bit in the INTRRXE register should be set (if an interrupt is required for this endpoint) and
the PERI_RXCSR register should be set as shown in
.
Table 5. PERI_RXCSR Register Bit Configuration for Isochronous OUT Transactions
Bit Position
Bit Field Name
Configuration
Bit 14
ISO
Set to 1 to enable isochronous protocol
Bit 13
DMAEN
Set to 1 if a DMA request is required for this endpoint
Bit 12
DISNYET
Ignored in isochronous transfers
Bit 11
DMAMODE
Always set this bit to 0
3.1.4.2.2
Operation
An Isochronous endpoint does not support data retries so, if a data overrun is to be avoided, there must
be space in the FIFO to accept a packet when it is received. The host will send one packet per frame (or
microframe in High-speed mode); however, the time within the frame can vary. If a packet is received near
the end of one frame(/microframe) and another arrives at the start of the next frame, there will be little time
to unload the FIFO. For this reason, double buffering of the endpoint is usually necessary.
An interrupt is generated whenever a packet is received from the host and the software may use this
interrupt to unload the packet from the FIFO and clear the RXPKTRDY bit in the PERI_RXCSR register
(bit 0) in the same way as for a Bulk Rx endpoint. As the interrupt could occur almost any time within a
frame(/microframe), depending on when the host has scheduled the transaction, the timing of FIFO unload
requests will probably be irregular. If the data sink for the endpoint is going to some external hardware, it
may be better to minimize the requirement for additional buffering by waiting until the end of each
frame(/microframe) before unloading the FIFO. This can be done by using either the SOF interrupt or the
external SOF_PULSE signal from the controller to trigger the unloading of the data packet. The
SOF_PULSE is generated once per frame(/microframe) when a SOF packet is received. (The controller
also maintains an external frame(/microframe) counter so it can still generate a SOF_PULSE when the
SOF packet has been lost.) The interrupts may still be used to clear the RXPKTRDY bit in PERI_RXCSR
and to check for data overruns/underruns.
3.1.4.2.3
Error Handling
If there is no space in the FIFO to store a packet when it is received from the host, the OVERRUN bit in
the PERI_RXCSR register (bit 2) will be set. This is an indication that the software is not unloading data
fast enough for the host. It is up to the application to determine how this error condition is handled.
If the controller finds that a received packet has a CRC error, it will still store the packet in the FIFO and
set the RXPKTRDY bit (bit 0 of PERI_RXCSR) and the DATAERROR bit (bit 3 of PERI_RXCSR). It is left
up to the application how this error condition is handled.
SPRUGH3 – November 2008
Universal Serial Bus (USB) Controller
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